Accurate VHDL Delay and Power Characterization of CMOS Logic Cells
نویسندگان
چکیده
This paper presents a model for characterizing delay and power for CMOS logic cells that accounts for input slope and output capacitance loading. A method for deriving the model parameters and VHDL modeling for simple logic gates is presented. The model makes feasible delay and power estimation at VHDL simulation speed, the errors of the model prediction are less than 5% of Spice results.
منابع مشابه
Design and Simulation of a 2GHz, 64×64 bit Arithmetic Logic Unit in 130nm CMOS Technology
The purpose of this paper is to design a 64×64 bit low power, low delay and high speed Arithmetic Logic Unit (ALU). Arithmetic Logic Unit performs arithmetic operation like addition, multiplication. Adders play important role in ALU. For designing adder, the combination of carry lookahead adder and carry select adder, also add-one circuit have been used to achieve high speed and low area. In mu...
متن کاملEfficient Delay Characterization Method to Obtain the Output Waveform of Logic Gates Considering Glitches
Accurate delay calculation of circuit gates is very important in timing analysis of digital circuits. Waveform shapes on the input ports of logic gates should be considered, in the characterization phase of delay calculation, to obtain accurate gate delay values. Glitches and their temporal effect on circuit gate delays should be taken into account for this purpose. However, the explosive numbe...
متن کاملOptimized Standard Cell Generation for Static CMOS Technology
Fabrication of an integrated circuit with smaller area, besides reducing the cost of manufacturing, usually causes a reduction in the power dissipation and propagation delay. Using the static CMOS technology to fabricate a circuit that realizes a specific logic function and occupies a minimum space, it must be implemented with continuous diffusion runs. Therefore, at the design stage, an Euleri...
متن کاملOptimized Standard Cell Generation for Static CMOS Technology
Fabrication of an integrated circuit with smaller area, besides reducing the cost of manufacturing, usually causes a reduction in the power dissipation and propagation delay. Using the static CMOS technology to fabricate a circuit that realizes a specific logic function and occupies a minimum space, it must be implemented with continuous diffusion runs. Therefore, at the design stage, an Euleri...
متن کاملPerformance evaluation of the CMOS Full adders in TDK 90 nm Technology
This paper presents power analysis of the full adder cells reported as having a low PDP (Power Delay Product), by means of speed, power consumption and area. These full adders were designed upon various logic styles to derive the sum and carry outputs. Two new high-speed and low-power full adder cells designed with an alternative internal logic structure and pass-transistor logic styles that le...
متن کامل